Field of the Invention
The invention relates to a method for reading and refreshing the data contents of a dynamic semiconductor memory having many volatile memory cells disposed in columns and rows in a matrix. The reading of data contents from addressed memory cells is done by at least two data buses, to which the data contents are applied word by word, and the refreshing of the data contents of the memory cells is effected by a refresh pulse.
In dynamic semiconductor memories, the storage of information is done by the application and removal of charges to and from a capacitor assigned to each memory cell. The capacitor is coupled to a selection transistor which is triggerable via a word line and by way of which the capacitor is charged and discharged. The information flows from and to the memory cell via a bit line that is also connected to the selection transistor. In reading, the addressed cell is switched to the bit line, which causes the charge ratios on the bit line to change. By activation of read amplifiers, the change in charge in the bit line is reinforced for outputting a logical 1 or logical 0. Over time, the capacitor is known to lose its charge because of current leakage, so that the information in the memory cell has to be refreshed at regular intervals. The signals and signal combinations for the functions of reading, writing and refreshing that are needed to trigger the dynamic semiconductor memory are standardized. One such standard, which is fundamental to the subject of the invention, with a very efficient method for reading and simultaneously refreshing data contents is known as the "enhanced data out" mode with a "hidden refresh" under the EDO specification. The enhanced data out mode enables rapid access to the data of a row, since the data, unlike most other data output modes, are not turned off upon deactivation of the column address signal. The currently present data thus remain active until the next data are applied to the output. As a result, the data are available for further processing, for instance by a processor. The hidden refresh was introduced to reduce hardware expense. Outside the semiconductor memory it is merely determined when a refresh is to be done. Which data word will be refreshed is determined inside the memory. To that end, an internal address counter is provided which is incremented by one upon each refresh instruction and outputs a counter address that is supplied as a row address to an internal logic circuit. For detecting a refresh instruction, a column address signal is activated before a row address signal, so that the function of a column address or row address can be allocated to an address present on the address bus. During the refreshment, the data word to be output is continuously applied actively to the data bus, and the processor can utilize the time for further processing the data word, while memory cells are being refreshed at the same time. In a dynamic semiconductor memory with two or more data buses, under the enhanced data out standard (EDO standard), one signal input for application of a column address signal is provided for every data bus. During an enhanced data out mode with hidden refresh, on the one hand only the column address signal to whose associated data bus a data word was last applied is active. The hidden refresh is initiated by a chronologically limited deactivation of the row address signal, in a passive state of at least one column address signal, which on the other hand causes deactivation of the data words on the data buses associated with the passive column address signals. Thus only the last data word applied to the data bus assigned to the active column address signal remains active and available to the processor, while the other data buses remain unused until the next data words to be read out are activated, and the turned off data words for a processor, for instance, are no longer available.